Forming transistor gate structures in a semiconductor using a mask layer over an insulating layer

ABSTRACT

A plurality of contact plugs to be connected to a drain region or a source region of each of transistors constituting a sub-word line driver that drives a sub-word line are formed, by using a SAC line technique of selectively etching an insulation layer that covers each of the transistors by using a mask having line-shaped openings provided across a portion in which the contact plugs of each of the transistors are to be formed.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending application Ser. No.13/358,928 filed on Jan. 26, 2012, which is a continuation ofapplication Ser. No. 12/696,627 filed on Jan. 29, 2010, which claimsforeign priority to Japanese patent application No. 2009-019788 filed onJan. 30, 2009. The entire content of each of these applications ishereby expressly incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device and amanufacturing method of a semiconductor memory device, and moreparticularly relates to a semiconductor memory device including aselect-line driving circuit for driving a select line and amanufacturing method of the semiconductor memory device.

2. Description of Related Art

In general, a DRAM (Dynamic Random Access Memory) has a hierarchicalword line structure. Japanese Patent Application Laid-open PublicationNo. 2006-270126 discloses an example of a DRAM configured by hierarchialhierarchical word lines.

When hierarchial hierarchical word lines are used, the word lines arehierarchized into main word lines that become high-order word lines andsub-word lines that become low-order word lines. Each sub-word line isconnected to a main word line by a sub-word line driving circuit, andwhen a main word line driving circuit and the sub-word line drivingcircuit are activated based on a row address input from outside, acorresponding sub-word line is also activated.

Because many memory cells are connected to the sub-word lines, atransistor constituting the sub-word line driving circuit is required tohave a relatively high driving capacity. Therefore, a current drivingcapacity needs to be secured by increasing a gate width of eachtransistor to some extent.

To secure a sufficient gate width, conventionally, an installation areaof a sub-word line driving circuit takes uses a large length in anextending a lateral direction (a row direction) of sub-word lines. Thisis because sub-word line driving circuits are arranged along a layoutdirection (a column direction) of the sub-word lines, there is no roomfor a large length of the installation area of the sub-word line drivingcircuits in the layout direction of the sub-word lines.

However, when the installation area of the sub-word line drivingcircuits is long in the row direction, the entire size of the DRAMnaturally becomes large. Therefore, it has been required to furtherdecrease a size of the installation area in the row direction withoutdegrading the performance of the sub-word line driving circuits.

Contact plugs that connect source/drain regions of each of transistorsconstituting the sub-word line driving circuit and the sub-word linesare formed by using a technique called a SAC (Self Aligned Contact) holetechnique. According to this technique, an upper surface and a sidesurface of a gate electrode are first covered with a gate gap and asidewall made of a silicon nitride film. The entire sense amplifier iscovered on this with a silicon oxide film. The silicon oxide film isselectively etched by using a mask, thereby providing holes on thesource/drain regions. Last, a conductive layer is embedded into thecontact holes, thereby forming the contact plugs in self alignment.

The SAC hole technique has this name because a mask used for the aboveselective etching has holes for respective contacts.

However, the above technique has a problem in that a distance between acontact plug and a gate electrode becomes long. That is, because contactholes are very narrow holes, it takes some time before sufficient holesare formed. This is because it takes time for etchant to move in narrowholes. Accordingly, to prevent gate electrodes from being damaged, agate gap and a sidewall need to have a large thickness to some extent.Consequently, a distance between a contact plug and a gate electrodebecomes long increases corresponding to the large thickness.

When a distance between a contact plug and a gate electrode can bereduced, the inside of the sub-word line driving circuit can have highdensity, and a size of an installation area of the sub-word line drivingcircuit in the row direction can be reduced without degrading theperformance of the sub-word line driving circuit.

The same can be also applied to other types of circuit that drivescircuits that drive select lines (word lines are also one type of selectlines) such as a column decoder that drives column select lines, notonly to the sub-word line driving circuits.

SUMMARY

In one embodiment, there is provided a manufacturing method of asemiconductor memory device including select-line driving circuits thatdrives select lines, each of the select-line driving circuits includinga plurality of transistors having source/drain regions, the methodcomprising:

forming a mask having a line-shaped opening provided across thesource/drain regions of each of the transistors; and

forming a plurality of contact plugs each electrically connected to anassociated one of the source/drain regions by using a SAC line techniqueof selectively etching an insulation layer that covers each of thetransistors by using the mask.

In another embodiment, there is provided a manufacturing method of asemiconductor memory device comprising: forming a plurality of gatestructures along an active region each included in an associated one oftransistors that drives a plurality of word lines to which memory cellsare connected, each of the gate structures having an upper surface andaside surface covered with an insulation film; covering the activeregion and the gate structures by an interlayer insulation layer;forming a mask layer on the interlayer insulation layer, the mask layerhaving line-shaped openings across a portion where a plurality ofcontact holes to expose a source region and a drain region of each ofthe transistors are to be formed; forming the plurality of contact holesby selectively removing the interlayer insulation layer by using themask layer and the insulation layer as a mask; and forming contact plugswithin the contact holes.

In still another embodiment, there is provided a semiconductor memorydevice comprising: a plurality of select lines each elongating in afirst direction, the select lines being arranged at a pitch P insubstantially parallel to each other in a second direction crossing thefirst direction; and a plurality of gate pattern sets, each of the gatepattern sets including at least two gate electrode patterns, the gateelectrode pattern sets being arranged in line in the first direction,the at least two gate electrode patterns being arranged in line in thesecond direction; each of the gate pattern sets having a length in thesecond direction that is equal to or smaller than six times of the pitchP; each of the gate electrode patterns in each of the gate patternsserving as gates of a plurality of transistors constituting twoselect-line driving circuits.

In still another embodiment, there is provided a semiconductor memorydevice comprising: a plurality of word lines each extending in a firstdirection, a pitch of the word lines in a memory-cell array region is P;and a plurality pair of gate electrode patterns arranged in the firstdirection, wherein each pair of gate electrode patterns being extendedto the first direction in parallel, a length of each pair of gateelectrode patterns in a second direction substantially perpendicular tothe first direction is equal to or less than 6×P, each of the gateelectrode patterns are serves serve as a first gate electrode of atransistor included in a first word-line driving circuit that drives oneof the word lines and a second gate electrode of another transistorincluded in a second word-line driving circuit that drives other one ofthe word lines.

In still another embodiment, there is provided a semiconductor memorydevice comprising: a signal line pattern including a plurality of signallines and having a pitch defined by a line and a space, each of thesignal lines being elongated in a first direction, the signal linesbeing arranged in substantially parallel to each other in a seconddirection crossing the first direction; and a transistor patterndisposed adjacently to the signal line pattern, the transistor patternincluding an active region, at least four gate electrodes overlaying theactive region with an intervention of gate insulating films, and sourceand drain regions formed in the active region, the at least four gateelectrodes being arranged in substantially parallel to each other in thesecond direction and elongated in the first direction, and the activeregion having a length in the second direction that is six times aslarge as the pitch.

According to the present invention, openings of a mask are provided in aline shape across plural contact plugs. Therefore, et chant etchant canefficiently move within contact holes, as compared with holes formed bythe SAC hole technique. Accordingly, a distance between a contact holeand a gate electrode can be reduced.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The above features and advantages of the present invention will be moreapparent from the following description of certain preferred embodimentstaken in conjunction with the accompanying drawings, in which:

FIG. 1 shows a configuration of a semiconductor memory device accordingto an embodiment of the present invention;

FIG. 2 shows a circuit configuration of the memory cell area accordingto an embodiment of the present invention;

FIG. 3 shows a layout of an active region K within the memory cell areaaccording to an embodiment of the present invention, and shows anenlarged view of an area A shown in FIG. 2;

FIG. 4 shows a circuit configuration of the memory cell according to anembodiment of the present invention;

FIG. 5 shows a detailed circuit configuration of the semiconductormemory device shown in FIG. 1;

FIG. 6 shows internal circuits of the sub-word line drivers shown inFIG. 5;

FIG. 7 shows a three-dimensional configuration of the sub-word linedriver according to an embodiment of the present invention;

FIG. 8A shows a plane pattern layout of the sub-word area according toan embodiment of the present invention, FIG. 8B shows a plane patternlayout of the sub-word area according to a comparative example;

FIG. 9A shows a wiring layout of the sub-word lines connected to thesub-word line drivers, on the plane pattern layout of the sub-word areashown in FIG. 8A, FIG. 9B shows a wiring layout of the sub-word linesconnected to the sub-word line drivers, on the plane pattern layout ofthe sub-word area shown in FIG. 8B;

FIG. 10 shows the gate electrode pattern relevant to the main word lineand surrounded diffusion layers of gate electrodes extracted from theplane layout pattern shown in FIG. 8A;

FIG. 11 is a cross-sectional view along a line B-B′ in FIG. 8A;

FIG. 12 is a cross-sectional view along a line B-B′ in FIG. 8A and showsa manufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 13 is a cross-sectional view along a line B-B′ in FIG. 8A and showsa manufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 14 is a cross-sectional view along a line B-B′ in FIG. 8A and showsa manufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 15 is a plan view of a part of the sub-word line driver and shows amanufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 16 is a plan view of a part of the sub-word line driver and shows amanufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 17 is a plan view of a part of the sub-word line driver and shows amanufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 18 is a cross-sectional view along a line B-B′ in FIG. 8A and showsa manufacturing processes of the sub-word line driver and peripheralwirings thereof;

FIG. 19 shows a circuit configuration of the column decoder according toa modification of an embodiment of the present invention;

FIG. 20A shows a plane pattern layout of the inverter circuit configuredby using the present invention;

FIG. 20B shows a plane pattern layout of a similar inverter circuitconfigured without using the present invention; and

FIGS. 21A and 21B show wiring layouts of a column select signal lineconnected to the inverter circuits shown in FIGS. 20A and 20B, on theplane pattern layouts of the inverter circuits, respectively.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of the present invention will be explained belowin detail with reference to the accompanying drawings.

FIG. 1 shows a configuration of a semiconductor memory device accordingto an embodiment of the present invention. This semiconductor memorydevice is a DRAM, and only a part of a configuration within a memory matof the DRAM is shown in FIG. 1.

As shown in FIG. 1, the semiconductor memory device according to thepresent embodiment has plural memory cell areas MCA arranged in a matrixshape. Sub-word areas SWD are provided between the memory cell areas MCAadjacent in an X direction. The sub-word areas SWD are also provided atoutside of the memory cell areas MCA positioned at the furthest end, andmain word areas MWD are further provided at outside of the sub-wordlines SWD. Sense amplifier areas SAA are provided between the memorycell areas MCA adjacent in a Y direction. Column decoders YDEC areprovided at outside of the memory cell areas MCA positioned at thefurthest end. The X direction is an extending direction of the sub-wordlines SWL, and coincides with a longitudinal direction of the senseamplifier areas SAA. The Y direction is an extending direction of thebit lines BL, and coincides with a longitudinal direction of thesub-word areas SWD.

FIG. 2 shows a circuit configuration of the memory cell area. As shownin FIG. 2, the memory cell area MCA includes: plural sub-word lines SWLarranged in the X direction; plural bit lines BL arranged in the Ydirection; and memory cells MC arranged at each intersection of thesub-word line SWL and the bit line BL. Numbers of the sub-word lines SWLand the bit lines BL shown in FIG. 2 are only exemplary, and the presentinvention is not particularly limited thereto.

Each sub-word line SWL is connected, at every other line, to eachsub-word line driver (sub-word line driving circuit) SWLD within thesub-word area SWD arranged at one side in the X direction, and to eachsub-word line driver SWLD within the sub-word area SWD arranged at theother side in the X direction.

Several sub-word lines SWL positioned at both ends of the Y directionare not used, and these become unused sub-word lines SWLZ. This isbecause process conditions at a manufacturing time are slightlydifferent between the end and the center of the memory cell areas MCA,and defective cells easily occur at the ends of the memory cell areaMCA. Therefore, memory cells connected to these unused sub-word linesSWLZ are handled as dummy cells DC. Because the unused sub-word linesSWLZ are fixed in a deactive state, the dummy cells DC are not connectedto the bit lines BL.

The dummy sub-word lines DSWL are arranged at every three sub-word linesSWL, in the memory cell area MCA. That is, a unit configuration of twosub-word lines SWL and one dummy sub-word line DSWL is repeatedlyarranged in the Y direction. Neither a memory cell MC nor a dummy cellDC is arranged at an intersection of the dummy sub-word line DSWL andthe bit line BL. That is, the dummy sub-word lines DSWL are dummywirings basically not contributing to the actual operation. These dummysub-word lines DSWL are provided because a layout having 6F² as anoccupied area of the memory cells MC is employed when a minimum processsize or minimum feature size (minimum process dimension) is F. Thisarrangement is explained in detail below.

FIG. 3 shows a layout of an active region K within the memory cell areaMCA, and shows an enlarged view of an area A shown in FIG. 2. Aninsulation layer is embedded into regions other than the active region Kfollowing the STI (Shallow Trench Isolation) method, thereby configuringan insulation dielectric region I.

As shown in FIG. 3, a plane shape of the active region K isapproximately rectangular. The active region K has a slight angle in alongitudinal direction relative to the Y direction. The active regions Kare arranged in rows along the X direction. Based on this configuration,two adjacent sub-word lines SWL pass always on the same active region.

One active region K includes two memory cells MC. When an occupied areaof one memory cell MC is 6F², lengths of the active region K in the Xand Y directions are about 2F and about 6F, respectively. A detailedconfiguration of the active region K is explained below. The activeregion K has three diffusion regions 1a to 1c, and the diffusion region1a positioned at the center is connected to a corresponding bit line BLvia a bit contact 2. The diffusion regions 1b and 1c positioned at bothends are connected to corresponding cell capacitors (not shown) via cellcontacts 3. Each one sub-word line SWL passes on an upper part betweenthe diffusion region 1a and the diffusion regions 1b and 1c,respectively. Accordingly, the two adjacent diffusion regions and thesub-word line SWL between these two diffusion regions constitute a celltransistor of the memory cells MC, and one active region K includes twomemory cells MC.

A distance between the sub-word lines SWL each passing between thediffusion region 1a and the diffusion region 1b and between thediffusion region 1a and the diffusion region 1c, respectively, is 2F. Onthe other hand, a minimum distance between the sub-word lines SWLbetween the active regions K adjacent in the Y direction is 4F, becausethe length of the active region K in the Y direction is about 6F asdescribed above. Therefore, a distance between the sub-word lines SWLwithin the active region K is different from a distance between thesub-word lines SWL between the active regions K. To secure asatisfactory process condition, it is preferable that wiring density ofthe sub-word lines SWL is set constant. In the present embodiment, toset constant the wiring density of the sub-word lines SWL, the dummysub-word line DSWL is arranged at every three sub-word lines SWL.

The bit lines BL are connected, at every other line, to each senseamplifier SA within the sense amplifier area SAA arranged at one side inthe Y direction and to each sense amplifier SA within the senseamplifier area SAA arranged at the other side in the Y direction (anopen bit line system).

Each sense amplifier SA is a circuit used to amplify a potentialdifference between the bit lines BL, and is connected to a pair of bitlines BL extended to the Y direction with the memory cell areas MCAadjacent in the Y direction. More specifically, each sense amplifier SAis connected to a pair of bit lines BL extended respectively to theinside of two memory cell areas MCA adjacent in mutually differentdirections from the viewpoint of the sense amplifier SA.

An operation of a semiconductor memory device is explained below whileexplaining an internal configuration of the memory cell MC. As shown inFIG. 2, many (256K, for example) memory cells MC are arranged in thememory cell area MCA. As shown in FIG. 4, each memory cell MC includes acell transistor Tr and a cell capacitor C connected in series betweenthe bit line BL and a plate wiring PL. Agate electrode of the celltransistor Tr is connected to a corresponding sub-word line SWL.Accordingly, when the sub-word line SWL becomes at a high level, acorresponding cell transistor Tr becomes on, and the cell capacitor C isconnected to a corresponding bit line BL.

First, the sub-word line driver SWLD selected corresponding to a rowaddress input from outside activates a corresponding sub-word line SWL.The cell transistor Tr is then turned on within many memory cells MCconnected to the sub-word line SWL, and becomes a selected state (areadable and writable state). That is, the sub-word line SWL is a selectline to select the memory cell MC.

In writing data into the memory cell MC, a high-order writing potentialVARY (1.4 V, for example) or a low-order writing potential VSSA (0 V,for example) is supplied to the cell capacitor C through the bit line BLcorresponding to data to be stored.

Meanwhile, in reading data from the memory cell MC, the bit line BL isprecharged at an intermediate potential, that is, (VARY-VSSA)/2 (0.7V,for example, and hereinafter simply referred to as “VARY/2”), andthereafter, the cell transistor Tr is turned on. Accordingly, when thehigh-order writing potential VARY is written in advance in the cellcapacitor C, a potential of the bit line BL slightly increases from theintermediate potential. When the low-order writing potential VSSA iswritten in advance in the cell capacitor C, a potential of the bit lineBL slightly decreases from the intermediate potential.

As explained above, in accessing the memory cell MC, the sub-word linedriver SWLD first drives the sub-word line SWL. The semiconductor memorydevice according to the present embodiment has a characteristic in thesub-word line driver SWLD and the manufacturing method thereof.Therefore, configurations of the sub-word line driver SWLD andperipheral circuit thereof are explained first, and a manufacturingmethod of the sub-word line driver SWLD is explained next.

FIG. 5 shows a detailed circuit configuration of the semiconductormemory device shown in FIG. 1. As shown in FIG. 1, a main word linedriver MLD is provided in a main word area MWD. The main word linedriver MLD is connected to a main word line MWLB, a sub-word-line selectsignal line AAFXT, and a word-line float-prevention signal line ARFXBprovided in the X direction, respectively. Letters “B” and “T” attachedto the end of each symbol of each line represent low active and highactive, respectively.

Within each sub-word area SWD, two sub-word line drivers SWLD areprovided per one main word line MWLB. Each sub-word line driver SWLD isconnected to one main word line MWLB, one sub-word line SWL, onesub-word-line select signal line AAFXT, and one word-linefloat-prevention signal line ARFXB, respectively.

One specific example is taken from FIG. 5. Within the sub-word area SWDat the center in FIG. 5, sub-word line drivers SWLD0 and SWLD1 areprovided for a main word line MWLB0. The sub-word line driver SWLD0 isconnected to the main word line MWLB0, a sub-word line SWL0, asub-word-line select signal line AAFXT0, and a word-linefloat-prevention signal line ARFXB0, respectively. The sub-word linedriver SWLD1 is connected to the main word line MWLB0, a sub-word lineSWL1, a sub-word-line select signal line AAFXT1, and a word-linefloat-prevention signal line ARFXB1, respectively.

Similarly, sub-word line drivers SWLD2 and SWLD3 are provided for a mainword line MWLB1. The sub-word line driver SWLD2 is connected to the mainword line MWLB1, a sub-word line SWL2, the sub-word-line select signalline AAFXT0, and the word-line float-prevention signal line ARFXB0,respectively. The sub-word line driver SWLD3 is connected to the mainword line MWLB1, a sub-word line SWL3, the sub-word-line select signalline AAFXT1, and the word-line float-prevention signal line ARFXB1,respectively.

Each sub-word line SWL provided within the sub-word area SWD isconnected to the sub-word lines SWL within two memory cell areas MCAadjacent to the sub-word area SWD.

The main word line MWLB and the sub-word line SWL constitute thehierarchical word line described above. That is, the main word linedriver MLD activates a corresponding main word line MWLB and acorresponding sub-word-line select signal line AAFXT, according to a rowaddress signal input from outside. Consequently, the sub-word linedriver SWLD connected to both activated lines activates a correspondingsub-word line SWL. By employing the hierarchical word line, the numberof memory cells MC selected at one time can be reduced as compared withthe number of selected memory cells when the main word line MWLB isdirectly connected to each memory cell MC.

FIG. 6 shows internal circuits of the sub-word line drivers SWLD0 toSWLD3 shown in FIG. 5. As shown in FIG. 6, the sub-word line driverSWLD0 has a P-channel MOS transistor Q0, and N-channel MOS transistorsQ1 and Q2. Gates of the transistors Q0 and Q1 are connected to the mainword line MWLB0. Drains of the transistors Q0, Q1, and Q2 are connectedto the sub-word line SWL0. A source of the transistor Q0 is connected tothe sub-word-line select signal line AAFXT0. A potential VKK (groundpotential) is supplied to sources of the transistors Q1 and Q2. Othersub-word line drivers SWLD1 to SWLD3 are also similar to the above,except a difference of symbols of transistors and connection lines.

An operation of the sub-word line driver SWLD is explained withreference to FIG. 6.

First, the main word line driver MLD (see FIG. 5) determines thesub-word line SWL to be selected, according to a row address signalinput from outside. The main word line driver MLD activates acorresponding main word line MWLB and a corresponding sub-word-lineselect signal line AAFXT, according to the determined sub-word line SWL.Explanations are continued below while assuming that the sub-word linedriver SWLD0 is selected. In this case, the main word line driver MLDactivates the main word line MWLB0 and the sub-word-line select signalline AAFXT0, and deactivates other main word lines MWLB and othersub-word-line select signal lines AAFXT.

Because the main word line MWLB is low active, a low signal is input toeach gate of the transistors Q0, Q1, Q3, and Q4 connected to the mainword line MWLB0 in an activated state. Therefore, the P-channel MOStransistors Q0 and Q3 are turned on, and the N-channel MOS transistorsQ1 and Q4 are turned off. Accordingly, the sub-word lines SWL0 and SWL1are connected to the sub-word-line select signal lines AAFXT0 andAAFXT1, respectively. Because the sub-word-line select signal line AAFXTis high active, the activated sub-word-line select signal line AAFXT0becomes a high state, and the non-activated sub-word-line select signalline AAFXT1 is in a low state. Therefore, the sub-word line SWL0 becomesa selected state (a state that the cell transistor connected to thesub-word line SWL0 is on), and the sub-word line SWL1 becomes anon-selected state (a state that the cell transistor connected to thesub-word line SWL1 is off).

On the other hand, a high signal is input to each gate of thetransistors Q6, Q7, Q9, and Q10 connected to the main word line MWLB1 inthe non-activated state. Therefore, the N-channel MOS transistors Q7 andQ10 are turned on, and the P-channel MOS transistors Q6 and Q9 areturned off. Accordingly, the potential VKK is supplied to the sub-wordlines SWL2 and SWL3, and these sub-word lines become in the non-selectedstate.

The word-line float-prevention signal line ARFXB is used to prevent apotential float of the sub-word lines SWL in the non-selected state.That is, when the word-line float-prevention signal line ARFXB0 is notactivated, for example, the transistors Q2 and Q8 become in the onstate, and the potential VKK is supplied to the sub-word lines SWL0 andSWL2 via the transistors Q2 and Q8. Accordingly, potentials of thesub-word lines SWL0 and SWL2 are more securely fixed to the potentialVKK. Because the word-line float-prevention signal line ARFXB is used toprevent a potential float of the sub-word lines SWL in this way,transistors having a smaller driving capacity than that of othertransistors can be used for the transistors Q2, Q5, Q8, and Q11connected to the word-line float-prevention signal line ARFXB.

A configuration of the transistor constituting the sub-word line driverSWLD is explained next.

FIG. 7 shows a three-dimensional configuration of the sub-word linedriver SWLD. FIG. 7 shows a three-dimensional configuration oftransistors constituting the sub-word line drivers SWLD0 to SWLD4 shownin FIG. 6. In FIG. 7, a plane S represents a surface of a P-typesemiconductor substrate on which the sub-word line drivers SWLD0 toSWLD4 are provided.

As shown in FIG. 7, an N-type region (NWELL) 11 is provided on thesurface S of the P-type semiconductor substrate. Four active regions K1to K4 are arranged in the X direction. The active regions K1 and K2 arepositioned at outside of the N-type region 11, and the active regions K3and K4 are positioned within the N-type region 11. These active regionsK1 to K4 are partitioned by an insulation layer (a dielectric isolationregion) embedded in the surface S of the P-type semiconductor substrate,in a similar manner to that of the active region K within the memorycell area MCA. FIG. 7 omits this insulation layer.

In the active region K1, two rows of n+ diffusion layers made of five n+diffusion layers 16a to 16e arranged at equal intervals along the Ydirection are arranged. Similarly, in the active region K2, two rows ofn+ diffusion layers made of five n+ diffusion layers 17a to 17e arrangedat equal intervals along the Y direction are arranged. In the activeregion K3, two rows of p+ diffusion layers made of five p+ diffusionlayers 18a to 18e arranged at equal intervals along the Y direction arearranged. In the active region K4, two rows of p+ diffusion layers madeof five p+ diffusion layers 19a to 19e arranged at equal intervals alongthe Y direction are arranged.

On the surface S of the P-type semiconductor substrate, gate electrodestructures G1 to G6 made of a conductive layer and an insulation layerare provided (an internal configuration of the gate electrode structureis described in detail later). In FIG. 7, while the gate electrodestructures G1 to G6 are isolated from the surface S to facilitate theunderstanding of a structure of the surface S, the gate electrodestructures G1 to G6 are actually contacted to the surface S via a gatedielectric film.

The gate electrode structure G1 has a rectangular plane having alongitudinal direction in the X direction, and is arranged between then+ diffusion layers 16a and 17a and the n+ diffusion layers 16b and 17b.Both ends of the gate electrode structure G1 in the longitudinaldirection are extended to above the dielectric isolation region.

The gate electrode structure G2 has a U-shaped plane having alongitudinal direction in the X direction. One of two straight lineportions extended to the X direction is arranged between the n+diffusion layer 16b and the n+ diffusion layer 16c, and the otherstraight line portion is arranged between the n+ diffusion layer 16c andthe n+ diffusion layer 16d. A portion extended to the Y direction ispartly extended to above the dielectric isolation region.

The gate electrode structure G3 has a U-shaped plane having alongitudinal direction in the X direction. One of two straight lineportions extended to the X direction is arranged between the n+diffusion layer 17b and the n+ diffusion layer 17c, and the otherstraight line portion is arranged between the n+ diffusion layer 17c andthe n+ diffusion layer 17d. A portion extended to the Y direction ispartly extended to above the dielectric isolation region.

As shown in FIG. 7, the active regions K1 and K2 have cuts C1 and C2immediately below two straight line portions extended to the X directionof the gate electrode structures G2 and G3. These cuts are provided tosubstantially shorten a channel width when the gate electrode structuresG2 and G3 function as gate electrodes of transistors.

The gate electrode structure G4 has a rectangular plane having alongitudinal direction in the X direction, and is arranged between then+ diffusion layers 16d and 17d and the n+ diffusion layers 16e and 17e.Both ends of the gate electrode structure G4 in the longitudinaldirection are extended to above the dielectric isolation region.

The gate electrode structure G5 has a U-shaped plane having alongitudinal direction in the X direction. One of two straight lineportions extended to the X direction is arranged between the p+diffusion layers 18a and 19b and the p+ diffusion layers 18b and 19b,and the other straight line portion is arranged between the p+ diffusionlayers 18b and 19b and the p+ diffusion layers 18c and 19c. A part of aportion extended to the Y direction, and each open end of two straightline portions extended to the X direction are extended to above thedielectric isolation region.

The gate electrode structure G6 has a U-shaped plane having alongitudinal direction in the X direction. One of two straight lineportions extended to the X direction is arranged between the p+diffusion layers 18c and 19c and the p+ diffusion layers 18d and 19d,and the other straight line portion is arranged between the p+ diffusionlayers 18d and 19d and the p+ diffusion layers 18e and 19e. A part of aportion extended to the Y direction, and each open end of two straightline portions extended to the X direction are extended to above thedielectric isolation region.

FIG. 8A shows a plane pattern layout of the sub-word area SWD. The planepattern in FIG. 8A corresponds to a configuration shown in FIG. 7 viewedfrom the above. In FIG. 8A, a boundary line (a dashed line) of theactive region is drawn above the gate electrode structure to facilitatethe understanding of a relationship between the gate electrode structureand the active region.

FIG. 9A shows a wiring layout of the sub-word lines SWL0 to SWL3connected to the sub-word line drivers SWLD0 to SWLD3, on the planepattern layout of the sub-word area SWD shown in FIG. 8A. In FIG. 9A,black circle marks provided in the sub-word lines SWL denote parts wherea diffusion layer is electrically in contact with the sub-word line SWL.For each of the main word line MWLB, the sub-word-line select signalline AAFXT, and the word-line float-prevention signal line ARFXB, only acontact point with a diffusion layer or with a gate electrode structureis shown by a hollow round mark.

Relationships between the transistors Q1 to Q12, the gate electrodestructures G1 to G6, the n+ diffusion layers, and the p+ diffusionlayers shown in FIG. 6 are explained below with reference to FIG. 8A andFIG. 9A. Thereafter, a plane pattern layout of the sub-word area SWD isexplained in detail.

First, the active regions K1 and K2 are mainly explained. The gateelectrode pattern G1 (a plane pattern corresponding to the gateelectrode structure G1; and this applies to the subsequent explanations)is connected to the main word line MWLB0 on the dielectric isolationregion, as shown in FIG. 9A. The n+ diffusion layers 16a and 16bpositioned at both sides of the gate electrode pattern G1 within thediffusion region K1 are connected to the potential VKK and the sub-wordline SWL1, respectively, as shown in FIG. 9A. Therefore, the gateelectrode pattern G1 and the n+ diffusion layers 16a and 16b function asthe transistor Q4. The gate electrode pattern G1, the n+ diffusion layer16a, and the n+ diffusion layer 16b constitute a gate, a source, and adrain of the transistor Q4, respectively.

Further, the n+ diffusion layers 17a and 17b positioned at both sides ofthe gate electrode pattern G1 within the diffusion region K2 areconnected to the potential VKK and the sub-word line SWL0, respectively,as shown in FIG. 9A. Therefore, the gate electrode pattern G1 and the n+diffusion layers 17a and 17b function as the transistor Q1. The gateelectrode pattern G1, the n+ diffusion layer 17a, and the n+ diffusionlayer 17b constitute a gate, a source, and a drain of the transistor Q1,respectively.

Next, the gate electrode pattern G4 is connected to the main word lineMWLB1 on the dielectric isolation region, as shown in FIG. 9A. The n+diffusion layers 16d and 16e positioned at both sides of the gateelectrode pattern G4 within the diffusion region K1 are connected to thesub-word line SWL3 and the potential VKK, respectively, as shown in FIG.9A. Therefore, the gate electrode pattern G4 and the n+ diffusion layers16d and 16e function as the transistor Q10. The gate electrode patternG4, the n+ diffusion layer 16d, and the n+ diffusion layer 16econstitute a gate, a drain, and a source of the transistor Q10,respectively.

The n+ diffusion layers 17d and 17e positioned at both sides of the gateelectrode pattern G4 within the diffusion region K2 are connected to thesub-word line SWL2 and the potential VKK, respectively, as shown in FIG.9A. Therefore, the gate electrode pattern G4 and the n+ diffusion layers17d and 17e function as the transistor Q7. The gate electrode patternG4, the n+ diffusion layer 17d, and the n+ diffusion layer 17econstitute a gate, a drain, and a source of the transistor Q7,respectively.

Next, the gate electrode pattern G2 is connected to the word-linefloat-prevention signal line ARFXB1 on the dielectric isolation region,as shown in FIG. 9A. One straight line portion at the gate electrodepattern G1 side out of two straight line portions extended to the Xdirection of the gate electrode pattern G2 is focused here. The n+diffusion layers 16b and 16c are arranged at both sides of this onestraight line portion, as shown in FIG. 8A. The n+ diffusion layer 16bconstitutes the drain of the transistor Q4 as described above, and then+ diffusion layer 16c is connected to the potential VKK as shown inFIG. 9A. Therefore, one straight line portion of the gate electrodepattern G2 and the n+ diffusion layers 16b and 16c function as thetransistor Q5. The gate electrode pattern G2, the n+ diffusion layer16b, and the n+ diffusion layer 16c constitute a gate, a drain, and asource of the transistor Q5, respectively.

The other straight line portion of the gate electrode pattern G2 (onestraight line portion at the gate electrode pattern G4 side out of thetwo straight line portions extended to the X direction of the gateelectrode pattern G2) is focused below. The n+ diffusion layers 16c and16d are arranged at both sides of the other straight line portion, asshown in FIG. 8A. The n+ diffusion layer 16c is connected to thepotential VKK as described above, and the n+ diffusion layer 16dconstitutes the drain of the transistor Q10 as described above.Therefore, the other straight line portion of the gate electrode patternG2 and the n+ diffusion layers 16c and 16d function as the transistorQ11. The gate electrode pattern G2, the n+ diffusion layer 16c, and then+ diffusion layer 16d constitute a gate, a source, and a drain of thetransistor Q11, respectively.

As described above, the active region K1 has the cut C1 (see FIG. 7)immediately below the gate electrode pattern G2. Therefore, channelregions of the transistors Q5 and Q11 are effectively very narrow.Although a driving capacity of the transistor Q5 becomes smaller thanthat when the cut C1 is not provided, the driving capacity is set smallby considering a balance of driving capacities, because the drivingcapacity of the transistors Q5 and Q11 can be small as described above.

The gate electrode pattern G3 is connected to the word-linefloat-prevention signal line ARFXB0 on the dielectric isolation region,as shown in FIG. 9A. One straight line portion at the gate electrodepattern G1 side out of two straight line portions extended to the Xdirection of the gate electrode pattern G3 is focused here. The n+diffusion layers 17b and 17c are arranged at both sides of this onestraight line portion, as shown in FIG. 8A. The n+ diffusion layer 17bconstitutes the drain of the transistor Q1 as described above, and then+ diffusion layer 17c is connected to the potential VKK as shown inFIG. 9A. Therefore, one straight line portion of the gate electrodepattern G3 and the n+ diffusion layers 17b and 17c function as thetransistor Q2. The gate electrode pattern G3, the n+ diffusion layer17b, and the n+ diffusion layer 17c constitute a gate, a drain, and asource of the transistor Q2, respectively.

The other straight line portion of the gate electrode pattern G3 (onestraight line portion at the gate electrode pattern G4 side out of thetwo straight line portions extended to the X direction of the gateelectrode pattern G3) is focused below. The n+ diffusion layers 17c and17d are arranged at both sides of the other straight line portion, asshown in FIG. 8A. The n+ diffusion layer 17c is connected to thepotential VKK as described above, and the n+ diffusion layer 17dconstitutes the drain of the transistor Q7 as described above.Therefore, the other straight line portion of the gate electrode patternG3 and the n+ diffusion layers 17c and 17d function as the transistorQ8. The gate electrode pattern G3, the n+ diffusion layer 17c, and then+ diffusion layer 17d constitute a gate, a source, and a drain of thetransistor Q8, respectively.

Next, the active regions K3 and K4 are mainly explained. The gateelectrode pattern G5 is connected to the main word line MWLB0 on thedielectric isolation region, as shown in FIG. 9A. Both the p+ diffusionlayers 18a and 18c positioned at both sides of the gate electrodepattern G5 within the diffusion region K3 are connected to thesub-word-line select signal line AAFXT1, as shown in FIG. 9A. Further,the p+ diffusion layer 18b positioned in the gate electrode pattern G5within the diffusion region K3 is connected to the sub-word line SWL1,as shown in FIG. 9A. Therefore, the gate electrode pattern G5 and the p+diffusion layers 18a to 18c function as the transistor Q3. The gateelectrode pattern G5, the p+ diffusion layers 18a and 18c, and the p+diffusion layer 18b constitute a gate, a source, and a drain of thetransistor Q3, respectively.

The p+ diffusion layers 19a and 19c positioned at both sides of the gateelectrode pattern G5 within the diffusion region K4 are connected to thesub-word-line select signal line AAFXT0, as shown in FIG. 9A. Further,the p+ diffusion layer 19b positioned in the gate electrode pattern G5within the diffusion region K4 is connected to the sub-word line SWL0,as shown in FIG. 9A. Therefore, the gate electrode pattern G5 and the p+diffusion layers 19a to 19c function as the transistor Q0. The gateelectrode pattern G5, the p+ diffusion layers 19a and 19c, and the p+diffusion layer 19b constitute a gate, a source, and a drain of thetransistor Q0, respectively.

The gate electrode pattern G6 is connected to the main word line MWLB1on the dielectric isolation region, as shown in FIG. 9A. Both the p+diffusion layers 18c and 18e positioned at both sides of the gateelectrode pattern G6 within the diffusion region K3 are connected to thesub-word-line select signal line AAFXT1, as shown in FIG. 9A. Further,the p+ diffusion layer 18d positioned in the gate electrode pattern G6within the diffusion region K3 is connected to the sub-word line SWL3,as shown in FIG. 9A. Therefore, the gate electrode pattern G6 and the p+diffusion layers 18a to 18c function as the transistor Q6. The gateelectrode pattern G6, the p+ diffusion layers 18a and 18c, and the p+diffusion layer 18b constitute a gate, a source, and a drain of thetransistor Q9, respectively.

The p+ diffusion layers 19c and 19e positioned at both sides of the gateelectrode pattern G6 within the diffusion region K4 are connected to thesub-word-line select signal line AAFXT0, as shown in FIG. 9A. Further,the p+ diffusion layer 19d positioned in the gate electrode pattern G6within the diffusion region K4 is connected to the sub-word line SWL2,as shown in FIG. 9A. Therefore, the gate electrode pattern G6 and the p+diffusion layers 19a to 19c function as the transistor Q6. The gateelectrode pattern G6, the p+ diffusion layers 19a and 19c, and the p+diffusion layer 19b constitute a gate, a source, and a drain of thetransistor Q6, respectively.

As shown in FIGS. 8A and 9A, in the transistors Q0, Q3, Q6, and Q9 asP-channel MOS transistors, a gate electrode length is about two timesthat in the transistors Q1, Q4, Q7, and Q10 as N-channel MOStransistors. This is to compensate for a difference between the drivingcapacity of the P-channel MOS transistors and the driving capacity ofthe N-channel MOS transistors, thereby taking a balance between thetransistors.

Relationships between the transistors Q1 to Q12, the gate electrodepatterns (gate electrode structures) G1 to G6, the n+ diffusion layers,and the p+ diffusion layers are as explained above. A plane patternlayout of the sub-word area SWD is explained next in detail.

FIG. 10 shows the gate electrode pattern relevant to the main word lineMWLB0 and surrounded diffusion layers of gate electrodes extracted fromthe plane layout pattern shown in FIG. 8A. As shown in FIG. 10, whenonly the main word line MWLB0 is focused, two sub-word line driversSWLD0 and SWLD1 connected to the main word line MWLB0 include a pair ofgate electrode patterns line-symmetric to a straight line L,respectively, and are configured by three gate-electrode pattern sets S1to S3 arranged in the X direction. The pair of gate electrode patternsare arranged in the X direction, and are arranged in parallel in the Ydirection.

As explained above, the two sub-word line drivers SWLD0 and SWLD1connected to the main word line MWLB0 are arranged within the regionslender in the X direction. When a pitch of the sub-word lines is P(=2F; F is a minimum process dimension), a length Ly of this region inthe Y direction becomes equal to or smaller than 6P (=12F), as can beunderstood from FIG. 9. This relationship of Ly≤6P is set because manysub-word line drivers SWLD need to be arranged in parallel within thesub-word area SWD. This relationship is explained in more detail. Thelength Ly in the Y direction permitted to the two sub-word line driversSWLD connected to one main word line MWLB is limited to a lengthcorresponding to the entire pitch of four sub-word lines and two dummysub-word lines DSWL, as can be understood from FIG. 2. On the otherhand, there is no such a limitation to a length Lx in the X direction.But the length Lx in the X direction in the present embodiment isshorter than that according to the conventional technique.

A difference between the present embodiment and the conventionaltechnique is explained below with reference to a comparative exampleachieved by the conventional technique. In the comparative exampledescribed below, an internal circuit configuration of the sub-word areaSWD is the same as that of the embodiment explained with reference toFIGS. 5 and 6. A driving capacity (=channel width of each transistor) ofeach transistor is also substantially the same as that of the presentembodiment.

FIG. 8B shows a plane pattern layout of the sub-word area SWD accordingto the comparative example. FIG. 9B shows a wiring layout of thesub-word lines SWL0 to SWL3 connected to the sub-word line drivers SWLD0to SWLD3, on the plane pattern layout of the sub-word area SWD shown inFIG. 8B.

As shown in FIGS. 9A and 9B, a length in the Y direction of a regionoccupied by the sub-word line drivers SWLD0 to SWLD3 is restricted to 12sub-word lines (=24F), in both the present embodiment and thecomparative example.

Meanwhile, a length in the X direction of the region occupied by thesub-word line drivers SWLD0 to SWLD3 in the comparative example islarger than the length in the present embodiment. As is clear from thecomparison between FIGS. 9A and 9B, this difference occurs because whilefour gate electrode patterns are arranged in parallel in the range of alength of 24F in the Y direction in the present embodiment, only twogate electrode patterns can be arranged in parallel in the same range inthe comparative example.

That is, according to the semiconductor memory device of the presentembodiment, four gate electrode patterns can be arranged in parallel inthe range of the length of 24F in the Y direction. Therefore, thesemiconductor memory device according to the present embodiment canfurther shorten the length Lx in the X direction of the region occupiedby the sub-word line drivers SWLD0 to SWLD3 without degrading theperformance of the sub-word line driver SWLD. The gate electrodepatterns can be arranged in this way because a SAC line technique isused to form contact plugs that connect diffusion layers and upper-layerwirings. Formation of contact plugs by the SAC line technique isexplained below while explaining a manufacturing process of the sub-wordline driver SWLD.

A cross-sectional view of the sub-word line driver SWLD in a completedstate is explained first. FIG. 11 is a cross-sectional view along a lineB-B′ in FIG. 8A. As shown in FIG. 11, an insulation layer 12 is embeddedin a surface of a P-type semiconductor layer 10, and a dielectricisolation region is formed by the insulation layer 12. A surface havingno insulation layer 12 becomes an active region. It is preferable thatthe insulation layer 12 is configured by a silicon oxide film.

As shown in FIG. 11, each of the gate electrode structures G1 to G3(also the gate electrode structures G4 to G6) is configured by alaminate of a gate dielectric film 13 and a gate electrode 14, a capdielectric film 15 provided on an upper surface of the laminate, and asidewall dielectric film 20 provided on a side surface of the laminate.It is preferable that polysilicon, a metal, or silicide, or a laminateof these materials is used as a material of the gate electrode 14. Also,it is preferable to use silicon oxide for the gate dielectric film 13.The cap dielectric film 15 and the sidewall dielectric film 20 areprovided to dielectrically isolate each adjacent layer from the gateelectrode 14. A silicon nitride film can be used for a material of thesefilms.

An interlayer dielectric film 22 is formed in about the same filmthickness as that of the gate electrode structures G1 to G3. Contactholes 25 shown in FIG. 11 are provided in the interlayer dielectric film22. Conductive contact plugs 26 and 27 are embedded in the contact holes25. The contact plugs 26 are drain contact plugs provided on a diffusionlayer constituting a drain region, and the contact plugs 27 are sourcecontact plugs provided on diffusion layers constituting a source region.It is preferable that a polysilicon conductor and a metal such astungsten are used for materials of the contact plugs 26 and 27.

Diffusion layers (n+ diffusion layers 16b and 16d in FIG. 11)constituting a drain region are connected to corresponding sub-wordlines SWL, by drain contact plugs 26 and word contact plugs 29 providedon an upper surface of the drain contact plugs 26. On the other hand,diffusion layers (n+ diffusion layers 16a, 16c, and 16e in FIG. 11)constituting a source region are connected to a ground plane 33(transistors Q1, Q2, Q4, Q5, Q7, Q8, Q10, and Q11) having the potentialVKK or the sub-word-line select signal line AAFXT (transistors Q0, Q3,Q6, and Q9), by the source contact plugs 27 and contact plugs 32provided on an upper surface of the source contact plugs 27.

A manufacturing process of the sub-word line driver SWLD is explainedbelow with reference to FIGS. 12 to 18.

FIGS. 12 to 14 and FIG. 18 are cross-sectional views along the line B-B′in FIG. 8A. FIGS. 15 to 17 are plan views near the gate electrodestructures G1 to G4 in FIG. 8A. These drawings show manufacturingprocesses of the sub-word line driver SWLD and peripheral wiringsthereof. A manufacturing process of portions of the transistors Q4, Q5,Q11, and Q10 is explained below with reference to these drawings andFIGS. 7 to 9.

First, a semiconductor substrate having the P-type semiconductor layer10 is prepared. As shown in FIG. 7, impurity is implanted into a regionin which a P-channel MOS transistor is to be formed, and the N-typeregion 11 is provided. As shown in FIG. 12, a dielectric isolationregion (the insulation layer 12) is provided to partition the activeregion K.

Next, as shown in FIG. 12, a silicon surface of the P-type semiconductorlayer 10 is oxidized by using a thermal oxidation method, therebyforming an insulation film of silicon oxide having a film thickness ofabout 5 nm. A conductive material of polysilicon or the like islaminated in a thickness of about 100 nm on this insulation film. Asilicon nitride film is formed in a film thickness of about 200 nm on anupper surface of this laminated film. These films are patterned in ashape as shown in FIGS. 7 to 9 by anisotropic etching using a maskpattern. By the above process, as shown in FIG. 12, plural laminates ofthe gate dielectric film 13, the gate electrode 14, and the capdielectric film 15 are formed on the semiconductor layer 10.

After the patterning is completed, n− diffusion layers 16aa to 16ea areformed on an exposed surface of the P-type semiconductor layer 10, asshown in FIG. 12. Impurity concentration of the n− diffusion layers 16aato 16ea formed at this stage is relatively low.

Next, a silicon nitride film is deposited on the entire surface by theCVD method, and this film is etched back, thereby forming the sidewalldielectric film 20 in a film thickness of about 20 nm on a side surfaceof the gate dielectric film 13, the gate electrode 14, and the capdielectric film 15, respectively, as shown in FIG. 13. Plural gateelectrode structures, each having its front surface and side surfacecovered by the insulation film, are formed above.

After the gate electrode structure is formed, an impurity ion isimplanted again, thereby forming the n+ diffusion layers 16a to 16e onthe exposed surface of the P-type semiconductor layer, as shown in FIG.13. Impurity concentration of the n+ diffusion layers 16a to 16e formedat this stage is relatively high. Before implanting the ion to form then+ diffusion layers 16a to 16e, a selective epitaxial layer can beformed by selectively epitaxially growing silicon on the n-diffusionlayers 16aa to 16ea. The n+ diffusion layers 16a to 16e are formed bydiffusing impurity via the selective epitaxial layer in this way.

After forming the n+ diffusion layers 16a to 16e, a silicon oxide filmis deposited in a film thickness of about 500 nm on the entire surface,thereby forming the insulation layer 22 shown in FIG. 13. The surface ofthe insulation layer 22 is flattened by using the CMP method or thelike.

FIG. 14 is a plan view of a transistor in a state that processing up tothe process shown in FIG. 13 is completed. FIG. 14 omits the insulationlayer 22. As shown in FIG. 14, the gate electrode structures G1 to G4 ina rectangular shape or a U shape are completed.

Next, as shown in FIG. 15, a mask layer 24 is formed on the insulationlayer 22. A so-called a hard mask is used for the mask layer 24. Themask layer 24 has line-shaped openings 24a provided across portions inwhich contact plugs of transistors are to be formed. That is, as shownin FIG. 11, the contact plugs 26 and 27 are formed on the diffusionlayers. The openings 24a are provided along the Y direction across thesecontact plugs.

The insulation layer 22 is selectively removed by selective etchingusing the mask layer 24 as a mask. That is, as described above, the capdielectric film 15 and the sidewall dielectric film 20 are made of asilicon nitride film. On the other hand the insulation layer 22 is asilicon oxide film. When a gas of a CF system is used as etchant, anetching rate of the silicon oxide film is larger than that of thesilicon nitride film. Therefore, only the insulation layer 22 can beselectively removed. Contact holes in a direction perpendicular to apaper surface are partitioned by the insulation film 22.

The mask layer 24 has the openings 24a having a line shape providedacross the plural contact plugs as described above. The openings areprovided based on the SAC line technique. As compared with a case ofproviding openings for each contact plug (the SAC hole technique),etchant can efficiently move within the contact holes. Therefore,etching can be performed efficiently. Consequently, time required foretching can be relatively short, and the cap dielectric film 15 and thesidewall dielectric film 20 can be formed relatively thin. The capdielectric film 15 and the sidewall dielectric film 20 can have athickness of about 20 nm as described above. On the other hand, when theSAC hole technique is used, a thickness of about 30 nm is necessary.

After the selective etching is finished, the contact holes 25 are formedon the n+ diffusion layers, as shown in FIG. 16, thereby exposing the n+diffusion layers. In case a selective epitaxial layer is formed, theepitaxial layer is exposed. In this state, a conductive layer ofpolysilicon or a laminated film of TiN (titanium nitride) and W(tungsten) or the like is deposited in a thickness of about 100 nm onthe entire surface, and a deposited result is polished by CMP until whena surface of the gate electrode structure is exposed. As a result, thecontact plugs 26 and 27 are formed within each contact hole 25, as shownin FIG. 17.

An interlayer dielectric film. 28 made of a silicon oxide film or thelike is formed in a thickness of about 200 nm on the entire surface, andthe interlayer dielectric film 28 is partly etched to expose the contactplugs 26, thereby forming the word contact plugs 29 in contact with thecontact plugs 26, as shown in FIG. 18. Although not shown, at thisstage, gate contact plugs to connect the gate electrodes to wirings onin an upper layer are also formed. The sub-word lines SWL are formed onthe interlayer dielectric film 28.

As shown in FIG. 11, an interlayer dielectric film 31 that covers theinterlayer dielectric film 28 and the sub-word lines SWL is formed.Holes piercing through the interlayer dielectric films 28 and 31 areprovided, and the contact plugs 32 are formed in the holes. Finally, theground plane 33 is formed on the interlayer dielectric film 31.

As explained above, in the manufacturing method of the semiconductormemory device according to the present embodiment, the openings 24a ofthe mask layer 24 are provided in a line shape across the contact plugs26 and 27. Therefore, as compared with the case of using the SAC holetechnique, etchant can efficiently move within the contact holes.Accordingly, time required for etching can be relatively short, and thecap dielectric film 15 and the sidewall dielectric film 20 can be formedrelatively thin. Consequently, a distance between the contact plugs 26and 27 and the gate electrodes 14 can be shortened. As a result, in thesemiconductor memory device according to the present embodiment, theentire DRAM can be downscaled, that is, the chip area is downsized.Specifically, a length in the X direction of the sub-word line driverSWLD can be reduced from a length according to the conventionaltechnique.

It is apparent that the present invention is not limited to the aboveembodiments, but may be modified and changed without departing from thescope and spirit of the invention.

The present invention is particularly suitable for application to aselect-line driving circuit that drives select lines. Examples of selectlines are column select lines and main word lines, in addition tosub-word lines. As a modification of the above embodiment, applicationof the present invention to the column decoder YDEC as a select-linedriving circuit that drives column select lines is explained.

FIG. 19 shows a circuit configuration of the column decoder YDEC. Asshown in FIG. 19, the column decoder YDEC is connected to many columnswitches YS.

The column switch YS is a switch circuit provided for each senseamplifier SA, and making and breaking a connection between the senseamplifier SA and a local I/O (LIO). Because the column switch YS isprovided for each sense amplifier SA, many column switches YS arearranged in the X direction in a similar manner to that of the senseamplifiers SA.

A NAND circuit 50 and inverter circuits 51 and 52 are arranged in seriesat a final stage of the column decoder YDEC. The inverter circuit 52drives a column select signal based on a predecoder signal input from apredecoder circuit (not shown) via the NAND circuit 50 and the invertercircuit 51, and is provided for each column switch YS. Therefore, manyinverter circuits 52 are also arranged in the X direction in a similarmanner to that of the sense amplifiers SA. A length of the invertercircuits 52 in the X direction is limited to a predetermined numbertimes a pitch of the bit lines BL. A length in the Y direction of theinverter circuit 52 configured by using the present invention can beshortened even in this limitation. This configuration is explained indetail below.

FIG. 20A shows a plane pattern layout of the inverter circuit 52configured by using the present invention. FIG. 20B shows a planepattern layout of a similar inverter circuit configured without usingthe present invention. FIGS. 20A and 20B show a P-channel MOS transistorTR0 and an N-channel MOS transistor TR1 constituting the invertercircuit 52, respectively in a similar manner to that shown in FIG. 8explained in the above embodiment.

FIGS. 21A and 21B show wiring layouts of a column select signal lineYSEL connected to the inverter circuits shown in FIGS. 20A and 20B, onthe plane pattern layouts of the inverter circuits, respectively.Reference symbols in FIGS. 21A and 21B designate like parts as those inFIG. 9A.

As shown in FIG. 20A, the transistor TR1 is configured by n+ diffusionlayers D1 provided on a surface of an active region K5 at outside of theN-type region 11, and a gate electrode structure G7 provided on thesurface. The transistor TR0 is configured by p+ diffusion layers D2provided on a surface of an active region K6 within the N-type region11, and a gate electrode structure G8 provided on the surface.

The gate electrode structure G7 is connected to an output of theinverter circuit 51, as shown in FIG. 21A. The n+ diffusion layers D1are connected to the column select signal line YSEL and a potential VSS.With this arrangement, the gate electrode structures G7 and the n+diffusion layers D1 function as the transistor TR1.

The gate electrode structure G8 is also connected to an output of theinverter circuit 51, as shown in FIG. 21A. The p+ diffusion layers D2are connected to the column select signal line YSEL and a potentialVPERI. With this arrangement, the gate electrode structures G8 and thep+ diffusion layers D2 function as the transistor TR0.

As shown in FIG. 20A, the gate electrode structures (gate electrodepatterns) G7 and G8 have four parallel straight line portions extendedto the Y direction, respectively, and the four straight line portionsare arranged in parallel in the X direction. On the other hand, in acomparative example shown in FIG. 20B, the gate electrode structures(gate electrode patterns) have two parallel straight line portionsextended to the Y direction, respectively, and the two straight lineportions are arranged in parallel in the X direction. Because of thisdifference, the inverter circuit 52 configured using the presentinvention has a shorter length in the Y direction than a direction inthe comparative example, despite the same effective channel widths. Thisis achieved by using the SAC line technique in forming the contact plugsthat connect the diffusion layers D1 and D2 and an upper layer wiring,by applying the present invention to the inverter circuit.

As described above, when the present invention is applied to the columndecoder YDEC as a circuit that drives the column select lines, a lengthof the column decoder YDEC in the Y direction can be shortened.

The main word line driver MLD (see FIG. 1) as a circuit that drives themain word line has a CMOS similar to the column decoder YDEC, at a laststage. By applying the present invention to the CMOS, a length of themain word line driver MLD in the X direction can be shortened.

In addition, while not specifically claimed in the claim section, theapplicant reserves the right to include in the claim section of theapplication at any appropriate time the following methods:

AA. A method of a semiconductor device, comprising:

forming in a semiconductor body source and drain regions of a pluralityof transistors constituting a select-line driving circuit that drives aselect-line in response to selection information;

forming an insulating layer over the semiconductor body including thesource and drain regions;

forming on the insulating layer a mask layer including a line-shapedopening such that the line-shaped opening is positioned over respectiveparts of the source and drain regions of the transistors with anintervention of the insulating layer; and

forming a plurality of contact plugs each electrically connected to anassociated one of the source and drain regions by use of a line SAC(Self-Align Contact) technique in which of the insulation layer isselectively removed by using the mask.

AA1. The method of the above AA, wherein the select-line is at least oneof word and column lines.

AA2. The method of the above AA, wherein the line-shaped opening isprovided along a direction substantially orthogonal to the select-line.

BB. A manufacturing method of a semiconductor device, comprising:

forming a plurality of gate structures on an active region in line, eachof the gate structures comprising a gate electrode and an insulatingfilm covering the gate electrode, the gate structures being respectivelyfor a plurality of transistors each driving an associated one of wordlines or column lines;

forming interlayer insulating layer over the active region the gatestructures;

forming a mask layer on the interlayer insulation layer, the mask layerhaving at least one opening, the opening being elongated to crossesrespective portions of the interlayer insulating layer active region inwhich a plurality of contact holes for source and drain regions of thetransistors are to be formed;

selectively removing the interlayer insulation layer by using the masklayer and the insulating film as a mask to form the contact holes; and

forming contact plugs in the contact holes.

BB1. The method of the above BB, wherein the opening is provided in adirection substantially orthogonal to the word or column lines.

BB2. The method of the above BB, wherein the gate structures areprovided in a direction substantially orthogonal to the word lines.

BB3. The method of the above BB2, wherein the gate structures areprovided to form a plurality of rows.

BB4. The method of the above BB, wherein each of the contact holes areformed between associated adjacent two of the gate structures.

What is claimed is:
 1. A method comprising: forming in a semiconductorbody source and drain regions of a plurality of transistors constitutinga select-line driving circuit that drives a select-line in response toselection information; forming an insulating layer over thesemiconductor body including the source and drain regions; forming onthe insulating layer a mask layer including a line-shaped opening suchthat the line-shaped opening is positioned over respective parts of thesource and drain regions of the transistors with an intervention of theinsulating layer; and forming a plurality of contact plugs eachelectrically connected to an associated one of the source and drainregions by use of a line SAC (Self-Align Contact) technique in which ofthe insulation layer is selectively removed by using the mask layer. 2.The method as claimed in claim 1, wherein the select-line is at leastone of word and column lines.
 3. The method as claimed in claim 1,wherein the line-shaped opening is provided along a directionsubstantially orthogonal to the select-line.
 4. A method comprising:forming a plurality of gate structures on an active region in line, eachof the gate structures comprising a gate electrode and an insulatingfilm covering the gate electrode, the gate structures being respectivelyfor a plurality of transistors each driving an associated one of wordlines or column lines; forming interlayer insulating layer over theactive region on which the gate structures are formed; forming a masklayer on the interlayer insulation layer, the mask layer having at leastone opening, the opening being elongated to cross respective portions ofthe gate structures on the active region in which a plurality of contactholes for source and drain region of the transistors are to be formed;selectively removing the interlayer insulation layer by using the masklayer and the insulating film as a mask to form the contact holes; andforming contact plugs in the contact holes.
 5. The method as claimed inclaim 4, wherein the opening is provided in a direction substantiallyorthogonal to the word of column lines.
 6. The method as claimed inclaim 4, wherein the gate structures are provided in a directionsubstantially orthogonal to the word lines.
 7. The method as claimed inclaim 6, wherein the gate structures are provided to form a plurality ofrows.
 8. The method as claimed in claim 4, wherein each of the contactholes are formed between associated adjacent two of the gate structures.9. A method comprising: forming a plurality of gate structures on anactive region in line, each of the gate structures comprising a gateelectrode and an insulating film covering the gate electrode, the gatestructures being respectively for a plurality of transistors, whereinthe plurality of transistors are formed in a memory core region; forminginterlayer insulating layer over the active region on which the gatestructures are formed; forming a mask layer on the interlayer insulationlayer, the mask layer having at least one opening, the opening beingelongated to cross respective portions of the gate structures on theactive region in which a plurality of contact holes for source and drainregion of the transistors are to be formed; selectively removing theinterlayer insulation layer by using the mask layer and the insulatingfilm as a mask to form the contact holes; and forming contact plugs inthe contact holes.
 10. The method as claimed in claim 9, wherein theplurality of transistors are formed in a sense amplifier area.
 11. Themethod as claimed in claim 9, wherein the memory core region includes atleast word line driving circuitry, decoding circuitry, sense amplifiercircuitry, and a memory cell area.
 12. The method as claimed in claim 9,wherein each of the contact holes are formed between associated adjacenttwo of the gate structures.